Features of this design:

• Up to 20MHz System Clock
  
  
• Programmable Divider to fine tune scanning rate to contact changeover time
  
  
• Support for three 8 x 8 matrices operated in parallel--large keyboards do not become slower.
  
  
• Efficient interrupt driven design for minimum processor overhead
  
  
• Full contact debouncing
  
  
• Internal I/O mapped address decoding
  
  
• Minimum external components
  
  
• 68 pin PLCC package for either surface mount or socketed applications
  
  
• 5 octave (61 note) velocity keyboard scanning with no further chips
  
  
• 3 x 61 note or 2 x 73/76/88 note or 1 x 192 note with the addition of low cost CMOS ICs.