Pin Description
Notes 1) There are Ground and Power pins on each side of the package. It is recommended that at least two sides are closely decoupled with multilayer ceramic 0.1µF capacitors. Internal Registers The Z80-DIO registers are I/O mapped and decoded as a block from 40h to 5Fh, addresses 40h to 87h are used and multiply mapped within the block. If finer mapping is required the A6 and A7 pins may be used as chip enables gated by external decoding logic. A second peripheral may be I/O mapped from 60h to 7Fh using the CS pin.
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Last updated: 25 January 2007 |